MCF52255

Product Summary

The MCF52255 is a reduced instruction set computing (RISC) microprocessor. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 512 Kbytes of flash memory and 64 Kbytes of static random access memory (SRAM).

Parametrics

MCF52255 absolute maximum ratings: (1)Supply voltage, VDD: -0.3 to +4.0 V; (2)Clock synthesizer supply voltage, VDDPLL: -0.3 to +4.0 V; (3)RAM standby supply voltage, VSTBY: +1.8 to 3.5 V; (4)USB standby supply voltage, VDDUSB: -0.3 to +4.0 V; (5)Digital input voltage, VIN: -0.3 to +4.0 V; (6)EXTAL pin voltage, VEXTAL: 0 to 3.3 V; (7)XTAL pin voltage, VXTAL: 0 to 3.3 V; (8)Instantaneous maximum current Single pin limit (applies to all pins), IDD: 25 mA; (9)Operating temperature range (packaged) TA/(TL - TH): -40 to 85 or 0 to 70℃; (10)Storage temperature range, Tstg: -65 to 150℃.

Features

MCF52255 features: (1)Version 2 ColdFire variable-length RISC processor core, Static operation, 32-bit address and data paths on-chip, Up to 80 MHz processor core frequency; (2)40 MHz or 33 MHz off-platform bus frequency; (3)Sixteen general-purpose, 32-bit data and address registers; (4)Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+); (5)Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 16μ16-32 or 32×32-32 operations; (6)Cryptographic Acceleration Unit (CAU); (7)Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions; (8)Support for DES, 3DES, AES, MD5, and SHA-1 algorithms; (9)System debug support; (10)Real-time trace for determining dynamic execution path; (11)Background debug mode (BDM) for in-circuit debugging (DEBUG_B+); (12)Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger; (13)On-chip memories; (14)Up to 64-Kbyte dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby power supply support for the first 16 Kbytes; (15)Up to 512 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses; (16)Power management; (17)Fully static operation with processor sleep and whole chip stop modes; (18)Rapid response to interrupts from the low-power sleep mode (wake-up feature); (19)Clock enable/disable for each peripheral when not used (except backup watchdog timer)Software controlled disable of external clock output for low-power consumption.

Diagrams