AM1705

Product Summary

The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. The AM1705 has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

Parametrics

AM1705 absolute maximum ratings: (1)Supply voltage ranges, core (CVDD, RVDD, PLL0_VDDA, USB0_VDDA12): -0.5 V to 1.4 V; I/O, 1.8V (USB0_VDDA18): -0.5 V to 2 V; I/O, 3.3V (DVDD, USB0_VDDA33): -0.5 V to 3.8V; (2)Input voltage ranges, VI I/O, 1.2V (OSCIN): -0.3 V to CVDD + 0.3V; VI I/O, 3.3V (Steady State): -0.3V to DVDD + 0.3V; VI I/O, 3.3V (Transient): DVDD + 20% up to 20% of Signal Period; VI I/O, USB 5V Tolerant Pins (USB0_DM, USB0_DP): 5.25V; VI I/O, USB0 VBUS: 5.50V; VO I/O, 3.3V (Steady State): -0.5 V to DVDD + 0.3V; (3)Output voltage ranges, VO I/O, 3.3V (Transient Overshoot/Undershoot): 20% of DVDD for up to 20% of the signal period; (4)Input or Output Voltages 0.3V above or below their respective power Clamp Current rails. Limit clamp current that flows through the I/O’s internal diode protection cells: ±20mA; (5)Storage temperature range, Tstg (default): -55℃ to 150℃; (6)Operating Junction Temperature ranges, TJ: Commercial (default): 0℃ to 90℃; Industrial (D version) -40℃ to 90℃ ; Extended (A version) -40℃ to 105℃.

Features

AM1705 features: (1)Applications, Industrial Automation; Home Automation; Test and Measurement; Portable Data Terminals; Eduational Consoles; Power Protection Systems; (2)375/456-MHz ARM926EJ-S RISC Core, 32-Bit and 16-Bit (Thumb) Instructions; Single Cycle MAC; ARM Jazelle Technology; EmbeddedICE-RT for Real-Time Debug; (3)ARM9 Memory Architecture, 16K-Byte Instruction Cache; 16K-Byte Data Cache; 8K-Byte RAM (Vector Table); 64K-Byte ROM; (4)Enhanced Direct-Memory-Access Controller 3 (EDMA3): 2 Transfer Controllers; 32 Independent DMA Channels; 8 Quick DMA Channels; Programmable Transfer Burst Size; (5)128K-Byte RAM Memory; (6)3.3V LVCMOS IOs (except for USB interface); (7)Two External Memory Interfaces: EMIFA, NOR (8-/16-Bit-Wide Data); NAND (8-/16-Bit-Wide Data); EMIFB, 16-Bit SDRAM With 256MB Address space; (8)Three Configurable 16550 type UART Modules: UART0 With Modem Control Signals; 16-byte FIFO; 16x or 13x Oversampling Option; (9)Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select; (10)Programmable Real-Time Unit Subsystem (PRUSS).

Diagrams