Product Summary

The EM638325 is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the EM638325 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Parametrics

EM638325 absolute maximum ratings: (1)VIN, VOUT, Input, Output Voltage: -1~4.6 V; (2)VDD, VDDQ, Power Supply Voltage: - 1~4.6 V; (3)TOPR, Operating Temperature: 0~70℃; (4)TSTG, Storage Temperature: -55~150℃; (5)TSOLDER, Soldering Temperature (10s): 260℃; (6)PD, Power Dissipation: 1 W; (7)IOUT, Short Circuit Output Current: 50 mA.

Features

EM638325 features: (1)Clock rate: 200/183/166/143/125/100 MHz; (2)Fully synchronous operation; (3)Internal pipelined architecture; (4)Four internal banks (512K x 32bit x 4bank); (5)Programmable Mode, CAS# Latency: 2 or 3; Burst Length: 1, 2, 4, 8, or full page; Burst Type: interleaved or linear burst; Burst-Read-Single-Write; (6)Burst stop function; (7)Individual byte controlled by DQM0-3; (8)Auto Refresh and Self Refresh; (9)4096 refresh cycles/64ms; (10)Single +3.3V ± 0.3V power supply; (11)Interface: LVTTL; (12)Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm pin pitch; (13)Lead Free Package available.

Diagrams

EM638325 block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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EM638325
EM638325

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Data Sheet

Negotiable 
EM638325TS/BG
EM638325TS/BG

Other


Data Sheet

Negotiable 
EM638325TS-6
EM638325TS-6

Other


Data Sheet

Negotiable